-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- PROGRAM "Quartus II"
-- VERSION "Version 7.2 Build 203 02/05/2008 Service Pack 2 SJ Full Version"

LIBRARY ieee;
USE ieee.std_logic_1164.all; 

LIBRARY work;

ENTITY mips IS 
	port
	(
		CLK :  IN  STD_LOGIC;
		RESET :  IN  STD_LOGIC;
		DI :  IN  STD_LOGIC_VECTOR(31 downto 0);
		INSTR :  IN  STD_LOGIC_VECTOR(31 downto 0);
		MEMWE :  OUT  STD_LOGIC;
		MEMRD :  OUT  STD_LOGIC;
		DADDR :  OUT  STD_LOGIC_VECTOR(31 downto 0);
		DATAO :  OUT  STD_LOGIC_VECTOR(31 downto 0);
		PC :  OUT  STD_LOGIC_VECTOR(31 downto 0)
	);
END mips;

ARCHITECTURE bdf_type OF mips IS 

component alu
	PORT(A : IN STD_LOGIC_VECTOR(31 downto 0);
		 B : IN STD_LOGIC_VECTOR(31 downto 0);
		 opcode : IN STD_LOGIC_VECTOR(4 downto 0);
		 negative : OUT STD_LOGIC;
		 overflow : OUT STD_LOGIC;
		 zero : OUT STD_LOGIC;
		 output : OUT STD_LOGIC_VECTOR(31 downto 0)
	);
end component;

component registerfile
	PORT(wen : IN STD_LOGIC;
		 clk : IN STD_LOGIC;
		 nReset : IN STD_LOGIC;
		 rsel1 : IN STD_LOGIC_VECTOR(4 downto 0);
		 rsel2 : IN STD_LOGIC_VECTOR(4 downto 0);
		 wdat : IN STD_LOGIC_VECTOR(31 downto 0);
		 wsel : IN STD_LOGIC_VECTOR(4 downto 0);
		 rdat1 : OUT STD_LOGIC_VECTOR(31 downto 0);
		 rdat2 : OUT STD_LOGIC_VECTOR(31 downto 0)
	);
end component;

component nextpc
	PORT(branch : IN STD_LOGIC;
		 jump : IN STD_LOGIC;
		 se : IN STD_LOGIC;
		 INSTR : IN STD_LOGIC_VECTOR(31 downto 0);
		 PC : IN STD_LOGIC_VECTOR(31 downto 0);
		 NPC : OUT STD_LOGIC_VECTOR(31 downto 0)
	);
end component;

component mux2x32
	PORT(sel : IN STD_LOGIC;
		 data0x : IN STD_LOGIC_VECTOR(31 downto 0);
		 data1x : IN STD_LOGIC_VECTOR(31 downto 0);
		 result : OUT STD_LOGIC_VECTOR(31 downto 0)
	);
end component;

component mux2x5
	PORT(sel : IN STD_LOGIC;
		 data0x : IN STD_LOGIC_VECTOR(4 downto 0);
		 data1x : IN STD_LOGIC_VECTOR(4 downto 0);
		 result : OUT STD_LOGIC_VECTOR(4 downto 0)
	);
end component;

component dff32e
	PORT(sclr : IN STD_LOGIC;
		 clock : IN STD_LOGIC;
		 enable : IN STD_LOGIC;
		 data : IN STD_LOGIC_VECTOR(31 downto 0);
		 q : OUT STD_LOGIC_VECTOR(31 downto 0)
	);
end component;

component maincontrol
	PORT(z : IN STD_LOGIC;
		 func : IN STD_LOGIC_VECTOR(5 downto 0);
		 opcode : IN STD_LOGIC_VECTOR(5 downto 0);
		 jump : OUT STD_LOGIC;
		 branch : OUT STD_LOGIC;
		 memtoreg : OUT STD_LOGIC;
		 writemem : OUT STD_LOGIC;
		 writereg : OUT STD_LOGIC;
		 regdes : OUT STD_LOGIC;
		 alusrcb : OUT STD_LOGIC;
		 se : OUT STD_LOGIC;
		 aluctr : OUT STD_LOGIC_VECTOR(4 downto 0)
	);
end component;

signal	aluctr :  STD_LOGIC_VECTOR(4 downto 0);
signal	aludatab :  STD_LOGIC_VECTOR(31 downto 0);
signal	alusrcb :  STD_LOGIC;
signal	branch :  STD_LOGIC;
signal	IMMSIGN :  STD_LOGIC_VECTOR(31 downto 16);
signal	jump :  STD_LOGIC;
signal	memtoreg :  STD_LOGIC;
signal	NPC :  STD_LOGIC_VECTOR(31 downto 0);
signal	PC_ALTERA_SYNTHESIZED :  STD_LOGIC_VECTOR(31 downto 0);
signal	R :  STD_LOGIC_VECTOR(31 downto 0);
signal	regdatab :  STD_LOGIC_VECTOR(31 downto 0);
signal	regdes :  STD_LOGIC;
signal	SE :  STD_LOGIC;
signal	writemem :  STD_LOGIC;
signal	WRITEREG :  STD_LOGIC;
signal	zero :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_0 :  STD_LOGIC_VECTOR(31 downto 0);
signal	SYNTHESIZED_WIRE_1 :  STD_LOGIC_VECTOR(31 downto 0);
signal	SYNTHESIZED_WIRE_2 :  STD_LOGIC_VECTOR(4 downto 0);
signal	SYNTHESIZED_WIRE_3 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_4 :  STD_LOGIC;

signal	GDFX_TEMP_SIGNAL_0 :  STD_LOGIC_VECTOR(31 downto 0);

BEGIN 
SYNTHESIZED_WIRE_3 <= '1';

GDFX_TEMP_SIGNAL_0 <= (IMMSIGN(31 downto 16) & INSTR(15 downto 0));


b2v_instalu : alu
PORT MAP(A => SYNTHESIZED_WIRE_0,
		 B => aludatab,
		 opcode => aluctr,
		 zero => zero,
		 output => R);

b2v_inst1 : registerfile
PORT MAP(wen => WRITEREG,
		 clk => CLK,
		 nReset => RESET,
		 rsel1 => INSTR(25 downto 21),
		 rsel2 => INSTR(20 downto 16),
		 wdat => SYNTHESIZED_WIRE_1,
		 wsel => SYNTHESIZED_WIRE_2,
		 rdat1 => SYNTHESIZED_WIRE_0,
		 rdat2 => regdatab);

b2v_inst12 : nextpc
PORT MAP(branch => branch,
		 jump => jump,
		 se => SE,
		 INSTR => INSTR,
		 PC => PC_ALTERA_SYNTHESIZED,
		 NPC => NPC);

b2v_inst13 : mux2x32
PORT MAP(sel => memtoreg,
		 data0x => DI,
		 data1x => R,
		 result => SYNTHESIZED_WIRE_1);

b2v_inst14 : mux2x5
PORT MAP(sel => regdes,
		 data0x => INSTR(15 downto 11),
		 data1x => INSTR(20 downto 16),
		 result => SYNTHESIZED_WIRE_2);

b2v_inst2 : dff32e
PORT MAP(sclr => RESET,
		 clock => CLK,
		 enable => SYNTHESIZED_WIRE_3,
		 data => NPC,
		 q => PC_ALTERA_SYNTHESIZED);

b2v_inst3 : maincontrol
PORT MAP(z => zero,
		 func => INSTR(5 downto 0),
		 opcode => INSTR(31 downto 26),
		 jump => jump,
		 branch => branch,
		 memtoreg => memtoreg,
		 writemem => writemem,
		 writereg => WRITEREG,
		 regdes => regdes,
		 alusrcb => alusrcb,
		 se => SE,
		 aluctr => aluctr);

SYNTHESIZED_WIRE_4 <= INSTR(15) AND SE;

b2v_inst5 : mux2x32
PORT MAP(sel => alusrcb,
		 data0x => regdatab,
		 data1x => GDFX_TEMP_SIGNAL_0,
		 result => aludatab);
IMMSIGN <= (SYNTHESIZED_WIRE_4 & SYNTHESIZED_WIRE_4 & SYNTHESIZED_WIRE_4 & SYNTHESIZED_WIRE_4 & SYNTHESIZED_WIRE_4 & SYNTHESIZED_WIRE_4 & SYNTHESIZED_WIRE_4 & SYNTHESIZED_WIRE_4 & SYNTHESIZED_WIRE_4 & SYNTHESIZED_WIRE_4 & SYNTHESIZED_WIRE_4 & SYNTHESIZED_WIRE_4 & SYNTHESIZED_WIRE_4 & SYNTHESIZED_WIRE_4 & SYNTHESIZED_WIRE_4 & SYNTHESIZED_WIRE_4);

MEMWE <= writemem;
DADDR <= R;
DATAO <= regdatab;
PC <= PC_ALTERA_SYNTHESIZED;

END; 